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* Enable metal tests (#8446)James Helferty (NVIDIA)2025-09-30
| | | | | | | | | | | | Enables all tests/metal/ tests that can be easily enabled. These tests were not originally designed as render tests; they are generally being enabled for pipecleaning purposes, and will not be rigorously testing the corresponding funcitonality. Where they cannot be enabled as render tests, and a metallib test wasn't already enabled, a metallib test was enabled instead (where possible). Fixes #7892
* Enable CUDA support for additional HLSL intrinsic tests (#8293)Harsh Aggarwal (NVIDIA)2025-09-04
| | | | | | | | | | | | | | | | | | | | | | | | Enable CUDA support for additional HLSL intrinsic tests by implementing missing functionality and fixing compiler bugs affecting CUDA targets. - Fix critical bug in InterlockedCompareStore64 where division used /4 instead of /8 for 64-bit types, causing incorrect memory addressing for all signed int 64_t atomics - Add signed int64_t atomic wrappers (atomicExch, atomicCAS) to CUDA prelu de that properly cast to/from unsigned types as required by CUDA's atomic API - Enable tests: atomic-intrinsics-64bit.slang - Implement CUDA support for QuadAny and QuadAll operations using warp shu ffle primitives (__shfl_sync with quad-level lane masking) - Add CUDA to quad_control capability definition in slang-capabilities.capdef - Add _slang_quadAny/_slang_quadAll helper functions to CUDA prelude - Enable tests: quad-control-comp-functionality.slang, subgroup-quad.slang --------- Co-authored-by: szihs <675653+szihs@users.noreply.github.com>
* render-test: Change D3D12 default to sm_6_5 (#8320)James Helferty (NVIDIA)2025-09-02
| | | | | | | | | Changes default for render-test to sm_6_5. Since sm_6_5 is the new default, remove the -use-dxil option, add -use-dxcb option Remove -use-dxil option from all test cases. Add -use-dxcb to two tests that needed it. Fixes #7611
* Enable tests for CUDA (#7593)Mukund Keshava2025-07-03
| | | | | | | | Enable intrinsic tests for cuda. Most of these tests were either disabled or just not enabled for cuda. Fixes #7592 Co-authored-by: Ellie Hermaszewska <ellieh@nvidia.com>
* Do not zero-initialize groupshared and rayquery variables (#4838)ArielG-NV2024-08-14
| | | | | | | | | | | | | | | | | | | | | | | * Do not zero-initialize groupshared and rayquery variables Fixes: #4824 `-zero-initialize` option will explicitly not: 1. Set any groupshared values to defaults 2. Set any rayQuery object to a default state (currently invalid code generation) * grammer * disallow groupshared initializers disallow groupshared initializers & adjust tests accordingly * remove disallowed groupshared-init expression * do not default init if non-copyable --------- Co-authored-by: Yong He <yonghe@outlook.com>
* SCCP instead of CFG since SCCP removes code of unused branches, not CFG (#4640)ArielG-NV2024-07-16
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* Implement non member function atomic texture support (#4544)ArielG-NV2024-07-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Implement non member function atomic texture support texture_buffer and texture1d Fixes: #4538 Related to: #4291, fixes `tests/compute/atomics-buffer.slang` Texture objects cannot use `__getMetalAtomicRef` to cast objects into atomic value type. [Texture objects mandate use of member functions](https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf#Texture%20Functions). The implementation is as follows: * We can detect texture object usage through checking for an `IRImageSubscript` Operation. `__isTextureAccess()` was added to evaluate if we have an `IRImageSubscript` operation at compile time (before `static_assert`). `__isTextureAccess()` only checks if we are targeting Metal. * We have all parameter data needed to call a texture atomic function embedded inside `IRImageSubscript`. `__extractTextureFromTextureAccess()` and `__extractCoordFromTextureAccess()` was added to extract this data for use with Metal atomics. Note: * Metal documentation has various incorrect details (function names) * Since we currently hardcode metal versions for compiling, the Metal compiler version was changed to target `Metal 3.1` (`slang-gcc-compiler-util.cpp`) * textures do not permit atomic float operations * add fallthrough attribute + fix bug with 'exchange instead of xor' + fix warning bug * incorrect function name fix * missing filecheck * disable atomics-buffer.slang compute test since GFX issue causing it to fail * Array support for metal interlockedAtomic and proper verification of texture with interlockedAtomic functions * Array support for metal interlockedAtomic * proper verification of texture with interlockedAtomic functions note: had to seperate many functions to allow forceInlining to run * missing getOperand(0) * push atomic fix for metal * fix atomic syntax for metal and hlsl emitting extra brackets (breaks tests) * test changes and meta changes 1. max is 8 rw textures with metal because Metal has this limit. Split up tests to not hit this limit 2. added back `[0]`...,`T` to test since this legalizes metal atomic intrinsic * macro'ify some of the atomic code 1. addresses review 2. makes code easier to modify in the future (rather than sifting through 1000 lines we can just look at ~10-30 * fix test 'check' * missing float support due to macro * add functions macro generates, `InternalAtomicOperationInfo` --------- Co-authored-by: Yong He <yonghe@outlook.com>
* Support 64bit HLSL atomic functions (#3957)Jay Kwak2024-04-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resolves #3951 This adds a few atomic functions for SM6.6. The spec can be found from here: https://microsoft.github.io/DirectX-Specs/d3d/HLSL_SM_6_6_Int64_and_Float_Atomics.html The new functions are: void InterlockedAdd(inout XXX dest, in int64_t value, out int64_t original_value); void InterlockedAdd(inout XXX dest, in uint64_t value, out uint64_t original_value); void InterlockedAnd(inout XXX dest, in uint64_t value, out uint64_t original_value); void InterlockedOr(inout XXX dest, in uint64_t value, out uint64_t original_value); void InterlockedXor(inout XXX dest, in uint64_t value, out uint64_t original_value); void InterlockedMin(inout XXX dest, in int64_t value, out int64_t original_value); void InterlockedMin(inout XXX dest, in uint64_t value, out uint64_t original_value); void InterlockedMax(inout XXX dest, in int64_t value, out int64_t original_value); void InterlockedMax(inout XXX dest, in uint64_t value, out uint64_t original_value); void InterlockedExchange(inout XXX dest, in float value, out float original_value); void InterlockedExchange(inout XXX dest, in int64_t value, out int64_t original_value); void InterlockedExchange(inout XXX dest, in uint64_t value, out uint64_t original_value); void InterlockedCompareStore(inout XXX dest, in int64_t compare_value, in int64_t value); void InterlockedCompareStore(inout XXX dest, in uint64_t compare_value, in uint64_t value); void InterlockedCompareStoreFloatBitwise(inout XXX dest, in float compare_value, in float value); void InterlockedCompareExchange(inout XXX dest, in int64_t compare_value, in int64_t value, out int64_t original_value); void InterlockedCompareExchange(inout XXX dest, in uint64_t compare_value, in uint64_t value, out uint64_t original_value); void InterlockedCompareExchangeFloatBitwise(inout XXX dest, in float compare_value, in float value, out float original_value); void RWByteAddressBuffer::InterlockedAnd64(in uint dest_offset, in uint64_t value, out uint64_t original_value); void RWByteAddressBuffer::InterlockedOr64(in uint dest_offset, in uint64_t value, out uint64_t original_value); void RWByteAddressBuffer::InterlockedXor64(in uint dest_offset, in uint64_t value, out uint64_t original_value); void RWByteAddressBuffer::InterlockedMin64(in uint dest_offset, in int64_t value, out int64_t original_value); void RWByteAddressBuffer::InterlockedMin64(in uint dest_offset, in uint64_t value, out uint64_t original_value); void RWByteAddressBuffer::InterlockedMax64(in uint dest_offset, in int64_t value, out int64_t original_value); void RWByteAddressBuffer::InterlockedMax64(in uint dest_offset, in uint64_t value, out uint64_t original_value); void RWByteAddressBuffer::InterlockedExchangeFloat(in uint dest_offset, in float value, out float original_value); void RWByteAddressBuffer::InterlockedExchange64(in uint dest_offset, in int64_t value, out int64_t original_value); void RWByteAddressBuffer::InterlockedExchange64(in uint dest_offset, in uint64_t value, out uint64_t original_value); void RWByteAddressBuffer::InterlockedCompareStore64(in uint dest_offset, in int64_t compare_value, in int64_t value); void RWByteAddressBuffer::InterlockedCompareStore64(in uint dest_offset, in uint64_t compare_value, in uint64_t value); void RWByteAddressBuffer::InterlockedCompareStoreFloatBitwise(in uint dest_offset, in float compare_value, in float value); void RWByteAddressBuffer::InterlockedCompareExchangeFloatBitwise(in uint dest_offset, in float compare_value, in float value, out float original_value);
* atomic intrinsic test (#3623)tgrimesnv2024-02-26
* Add first draft of atomic intrinsic test * Disable CUDA in atomic intrinsic test --------- Co-authored-by: Yong He <yonghe@outlook.com>