diff options
| -rw-r--r-- | source/slang/slang-capabilities.capdef | 5 | ||||
| -rw-r--r-- | source/slang/slang-emit-hlsl.cpp | 6 | ||||
| -rw-r--r-- | tests/compute/logic-no-short-circuit-evaluation.slang | 4 |
3 files changed, 15 insertions, 0 deletions
diff --git a/source/slang/slang-capabilities.capdef b/source/slang/slang-capabilities.capdef index 8f6aa254c..b50519a72 100644 --- a/source/slang/slang-capabilities.capdef +++ b/source/slang/slang-capabilities.capdef @@ -219,6 +219,11 @@ def _sm_6_9 : _sm_6_8; /// [Version] def hlsl_nvapi : hlsl; + +/// Represet HLSL compatibility support. +/// [Version] +def hlsl_2018 : _sm_5_1; + /// Represents capabilities required for DXIL Library compilation. /// [Version] alias dxil_lib = _sm_6_3; diff --git a/source/slang/slang-emit-hlsl.cpp b/source/slang/slang-emit-hlsl.cpp index 2d963866d..3813cf9cb 100644 --- a/source/slang/slang-emit-hlsl.cpp +++ b/source/slang/slang-emit-hlsl.cpp @@ -826,6 +826,9 @@ bool HLSLSourceEmitter::tryEmitInstExprImpl(IRInst* inst, const EmitOpInfo& inOu auto targetProfile = getTargetProgram()->getOptionSet().getProfile(); if (targetProfile.getVersion() < ProfileVersion::DX_6_0) return false; + auto targetCaps = getTargetReq()->getTargetCaps(); + if (targetCaps.implies(CapabilityAtom::hlsl_2018)) + return false; if (as<IRBasicType>(inst->getDataType())) return false; @@ -851,6 +854,9 @@ bool HLSLSourceEmitter::tryEmitInstExprImpl(IRInst* inst, const EmitOpInfo& inOu auto targetProfile = getTargetProgram()->getOptionSet().getProfile(); if (targetProfile.getVersion() < ProfileVersion::DX_6_0) return false; + auto targetCaps = getTargetReq()->getTargetCaps(); + if (targetCaps.implies(CapabilityAtom::hlsl_2018)) + return false; if (as<IRBasicType>(inst->getDataType())) return false; diff --git a/tests/compute/logic-no-short-circuit-evaluation.slang b/tests/compute/logic-no-short-circuit-evaluation.slang index 74351a505..ea2b7a0c3 100644 --- a/tests/compute/logic-no-short-circuit-evaluation.slang +++ b/tests/compute/logic-no-short-circuit-evaluation.slang @@ -1,4 +1,5 @@ //TEST(compute):SIMPLE(filecheck=SM5):-target hlsl -profile cs_5_1 -entry computeMain +//TEST(compute):SIMPLE(filecheck=HLSL2018):-target hlsl -profile cs_6_0 -capability hlsl_2018 -entry computeMain //TEST(compute):SIMPLE(filecheck=SM6):-target hlsl -profile cs_6_0 -entry computeMain //TEST(compute):SIMPLE(filecheck=WGS):-target wgsl -stage compute -entry computeMain //TEST(compute):SIMPLE(filecheck=MTL):-target metal -stage compute -entry computeMain @@ -29,6 +30,7 @@ void computeMain(int3 dispatchThreadID : SV_DispatchThreadID) // No short-circuiting for vector types //SM5:(all({{.*}}&& + //HLSL2018:(all({{.*}}&& //SM6:(all(and( //WGS:(all(select(vec2<bool>(false), //MTL:(all({{.*}}&& @@ -40,6 +42,7 @@ void computeMain(int3 dispatchThreadID : SV_DispatchThreadID) // Intentionally using non-boolean type for testing. //SM5:(all({{.*}}|| + //HLSL2018:(all({{.*}}|| //SM6:(or(vector<bool,2>( //WGS:(select({{.*}}, vec2<bool>(true), vec2<bool>( //MTL:(all(bool2({{.*}}|| @@ -49,6 +52,7 @@ void computeMain(int3 dispatchThreadID : SV_DispatchThreadID) } //SM5:(all({{.*}}?{{.*}}: + //HLSL2018:(all({{.*}}?{{.*}}: //SM6:(all(select( //WGS:(all(select(vec2<bool>(false), //MTL:(all(select(bool2(false) |