diff options
| -rw-r--r-- | docs/user-guide/a3-02-reference-capability-atoms.md | 9 | ||||
| -rw-r--r-- | source/slang/hlsl.meta.slang | 15 | ||||
| -rw-r--r-- | source/slang/slang-capabilities.capdef | 12 | ||||
| -rw-r--r-- | tests/spirv/double-atomic-add-byte-address-buffer.slang | 12 |
4 files changed, 48 insertions, 0 deletions
diff --git a/docs/user-guide/a3-02-reference-capability-atoms.md b/docs/user-guide/a3-02-reference-capability-atoms.md index f8f1b8eb7..9f673eaf8 100644 --- a/docs/user-guide/a3-02-reference-capability-atoms.md +++ b/docs/user-guide/a3-02-reference-capability-atoms.md @@ -407,6 +407,9 @@ Extensions `spvAtomicFloat16AddEXT` > Represents the SPIR-V capability for atomic float 16 add operations. +`spvAtomicFloat64AddEXT` +> Represents the SPIR-V capability for atomic float 64 add operations. + `spvInt64Atomics` > Represents the SPIR-V capability for 64-bit integer atomics. @@ -416,6 +419,9 @@ Extensions `spvAtomicFloat16MinMaxEXT` > Represents the SPIR-V capability for atomic float 16 min/max operations. +`spvAtomicFloat64MinMaxEXT` +> Represents the SPIR-V capability for atomic float 64 min/max operations. + `spvDerivativeControl` > Represents the SPIR-V capability for 'derivative control' operations. @@ -684,6 +690,9 @@ Compound Capabilities `cpp_cuda_spirv` > CPP, CUDA and SPIRV code-gen targets +`cuda_spirv` +> CUDA and SPIRV code-gen targets + `cpp_cuda_glsl_spirv` > CPP, CUDA, GLSL and SPIRV code-gen targets diff --git a/source/slang/hlsl.meta.slang b/source/slang/hlsl.meta.slang index 7c18f4717..39957f7ce 100644 --- a/source/slang/hlsl.meta.slang +++ b/source/slang/hlsl.meta.slang @@ -4425,6 +4425,21 @@ ${{{{ } } + [require(cuda, cuda_sm_6_0)] + [require(spirv, spvAtomicFloat64AddEXT)] + void InterlockedAddF64(uint byteAddress, double valueToAdd, out double originalValue) + { + __target_switch + { + case cuda: __intrinsic_asm "(*$3 = atomicAdd($0._getPtrAt<double>($1), $2))"; + default: + { + let buf = __getEquivalentStructuredBuffer<double>(this); + originalValue = __atomic_add(buf[byteAddress / 8], valueToAdd); + return; + } + } + } // FP16x2 /// @internal diff --git a/source/slang/slang-capabilities.capdef b/source/slang/slang-capabilities.capdef index 801d54eca..ed286eb86 100644 --- a/source/slang/slang-capabilities.capdef +++ b/source/slang/slang-capabilities.capdef @@ -254,6 +254,10 @@ alias cpp_cuda = cpp | cuda; /// [Compound] alias cpp_cuda_spirv = cpp | cuda | spirv; +/// CUDA and SPIRV code-gen targets +/// [Compound] +alias cuda_spirv = cuda | spirv; + /// CPP, CUDA, GLSL and SPIRV code-gen targets /// [Compound] alias cpp_cuda_glsl_spirv = cpp | cuda | glsl | spirv; @@ -522,6 +526,10 @@ def spvAtomicFloat32AddEXT : SPV_EXT_shader_atomic_float_add; /// [EXT] def spvAtomicFloat16AddEXT : SPV_EXT_shader_atomic_float16_add; +/// Represents the SPIR-V capability for atomic float 64 add operations. +/// [EXT] +def spvAtomicFloat64AddEXT : SPV_EXT_shader_atomic_float_add; + /// Represents the SPIR-V capability for 64-bit integer atomics. /// [EXT] def spvInt64Atomics : _spirv_1_0; @@ -534,6 +542,10 @@ def spvAtomicFloat32MinMaxEXT : SPV_EXT_shader_atomic_float_min_max; /// [EXT] def spvAtomicFloat16MinMaxEXT : SPV_EXT_shader_atomic_float_min_max; +/// Represents the SPIR-V capability for atomic float 64 min/max operations. +/// [EXT] +def spvAtomicFloat64MinMaxEXT : SPV_EXT_shader_atomic_float_min_max; + /// Represents the SPIR-V capability for 'derivative control' operations. /// [EXT] def spvDerivativeControl : _spirv_1_0; diff --git a/tests/spirv/double-atomic-add-byte-address-buffer.slang b/tests/spirv/double-atomic-add-byte-address-buffer.slang new file mode 100644 index 000000000..1b4a455ee --- /dev/null +++ b/tests/spirv/double-atomic-add-byte-address-buffer.slang @@ -0,0 +1,12 @@ +//TEST:SIMPLE(filecheck=CHECK): -target spirv + +// CHECK: OpAtomicFAddEXT + +RWByteAddressBuffer bab; + +[numthreads(1, 1, 1)] +void computeMain() +{ + double d; + bab.InterlockedAddF64(0, 1.0, d); +}
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