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| author | Ellie Hermaszewska <ellieh@nvidia.com> | 2023-09-05 23:26:59 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-05 23:26:59 +0800 |
| commit | 2c2294d3310b24fd73cd41ec51338a736f3a2886 (patch) | |
| tree | 0e02393fa772e7741eb38079a79f5cacaa1ba7b0 /tests/language-feature | |
| parent | 641f7bdc4ea4f75385c30d833cce4619a411ec67 (diff) | |
SPIR-V image operations (#3163)
* Add __truncate and __sampledType for spirv_asm
Allows some texture tests to start passing
* add __isVector
Currently unused
* Add 1-vector legalization pass (WIP)
* Add capabilities for image types
* neaten instruction dumping
* add 1-vector test
* Add a couple of cases to vec1 legalization
* Remove texture tests from expected failures
* comment
* regenerate vs projects
* Remove redundant define form synchapi emulation
* refactoring image methods
* All sample functions refactored
* Remove incorrect glsl intrinsics
Partially addresses https://github.com/shader-slang/slang/issues/3174
* __subscript image ops via writing funcs
* Extract texture struct writing from core.meta.slang
* Abstract out cuda intrinsic
* Remvoe erroneous call to opDecorateIndex
* spirv asm IR utils
* Correct position of loads for SPIR-V asm inst operands
* Raise constructors to global scope during spir-v legalization
* Correct snippet output
* Implement most texture sampling ops for SPIR-V
* Legalize 1-vectors for glsl too
* Make SPIR-V inst operands non-hoistable
* Better 1-vector legalization
* Put textures in ptrs for spirv
* insert missing break
* Add vec1 legalization test
* Add some missing pieces to slang-ir-insts
* Greatly neaten vec1 legalization
* a
* Neaten vec1 legalization
* Add image read and write intrinsics for spir-v
* Squash warnings
* regenerate vs projects
* Drop redundant guards
* Drop 5 tests from expected failure list
* Inst numbering changes to cross compile tests
* vec1 legalization tests only on vk
* Correct location of asm op emit
* Inline constant in spirv-asm
* Correct signedness for lane in wave intrinsics
* Extract element from float1 for cuda
* squash warnings
* Neaten spirv-emit
* dedupe more capabilities
* warnings
* neaten assert
* comments
* comments
Diffstat (limited to 'tests/language-feature')
| -rw-r--r-- | tests/language-feature/1-vector.slang | 19 | ||||
| -rw-r--r-- | tests/language-feature/spirv-asm/truncate.slang | 62 |
2 files changed, 81 insertions, 0 deletions
diff --git a/tests/language-feature/1-vector.slang b/tests/language-feature/1-vector.slang new file mode 100644 index 000000000..bb8cedf3c --- /dev/null +++ b/tests/language-feature/1-vector.slang @@ -0,0 +1,19 @@ +//TEST(compute):COMPARE_COMPUTE(filecheck-buffer=CHECK):-shaderobj +//TEST(compute):COMPARE_COMPUTE(filecheck-buffer=CHECK):-dx12 -use-dxil -shaderobj +//TEST(compute):COMPARE_COMPUTE(filecheck-buffer=CHECK):-cpu -shaderobj +//TEST(compute):COMPARE_COMPUTE(filecheck-buffer=CHECK):-vk -shaderobj + +//TEST_INPUT:ubuffer(data=[1 2 3 4], stride=4):out,name=outputBuffer +RWStructuredBuffer<int> outputBuffer; + +// CHECK: 0 +// CHECK-NEXT: 1 +// CHECK-NEXT: 2 +// CHECK-NEXT: 3 + +[numthreads(4, 1, 1)] +void computeMain(uint3 dispatchThreadID : SV_DispatchThreadID) +{ + vector<int,1> i = vector<int,1>(dispatchThreadID.x); + outputBuffer[i.x] = i.x; +} diff --git a/tests/language-feature/spirv-asm/truncate.slang b/tests/language-feature/spirv-asm/truncate.slang new file mode 100644 index 000000000..9837890f5 --- /dev/null +++ b/tests/language-feature/spirv-asm/truncate.slang @@ -0,0 +1,62 @@ +//TEST(compute):COMPARE_COMPUTE(filecheck-buffer=CHECK):-vk -shaderobj -emit-spirv-directly -output-using-type + +//TEST_INPUT:ubuffer(data=[1 2 3 4], stride=4):out,name=outputBuffer +RWStructuredBuffer<int> outputBuffer; + +// CHECK: 8 +// CHECK-NEXT: 13 +// CHECK-NEXT: 18 +// CHECK-NEXT: 23 + +// +// This test tests the __truncate operator +// +[numthreads(4, 1, 1)] +void computeMain(uint3 dispatchThreadID : SV_DispatchThreadID) +{ + int i = dispatchThreadID.x; + int n = outputBuffer[i]; + + int scalar = n; + + // 1-vectors are not valid in SPIR-V + // vector<int, 1> vector1 = vector<int, 1>(n); + + vector<int, 4> vector4 = n + vector<int, 4>(0,1,2,3); + //int expected = 0 + n + n + (n + (n+1) + (n+2)); + + int r = 0; + spirv_asm + { + // scalar to scalar + __truncate $$int %a1 $$int $scalar; + %r1 : $$int = OpIAdd %a1 $r; + + // scalar to 1-vector + // __truncate $$vector<int,1> %a2 $$int $scalar; + // %x1 : $$int = OpCompositeExtract %a2 0; + // %r2 : $$int = OpIAdd %x1 %r1; + %r2 : $$int = OpCopyObject %r1; + + // 1-vector to scalar + // __truncate $$int %a3 $$vector<int,1> $vector1; + // %r3 : $$int = OpIAdd %a3 %r2; + %r3 : $$int = OpCopyObject %r2; + + // n-vector to scalar + __truncate $$int %a4 $$vector<int,4> $vector4; + %r4 : $$int = OpIAdd %a4 %r3; + + // n-vector to m-vector + __truncate $$vector<int,3> %a5 $$vector<int,4> $vector4; + %x2 : $$int = OpCompositeExtract %a5 0; + %x3 : $$int = OpCompositeExtract %a5 1; + %x4 : $$int = OpCompositeExtract %a5 2; + %r5 : $$int = OpIAdd %x2 %r4; + %r6 : $$int = OpIAdd %x3 %r5; + %r7 : $$int = OpIAdd %x4 %r6; + + OpStore &r %r7 + }; + outputBuffer[i] = r; +} |
