diff options
| author | Tim Foley <tfoley@nvidia.com> | 2017-07-17 09:26:53 -0700 |
|---|---|---|
| committer | Tim Foley <tfoley@nvidia.com> | 2017-07-17 09:30:24 -0700 |
| commit | f881f52f6c34dbc2aa0a0701d6600467fae5a5ee (patch) | |
| tree | 9fc05221b73181c906e37a62b0fd0da3552660fe /tests/bugs/gh-103.slang.expected | |
| parent | fdab35e93082d6da4f9dbb4b6ec7b4c6dbce831c (diff) | |
Add explicit operator overloads for scalar/matrix cases
Fixes #103
- Previously I was relying on scalar-to-vector promotion to pick the right type in these cases, but I hadn't implemented scalar-to-matrix promotion (I should...)
- Rather than relying on promotion behavior, this change goes ahead and adds explicit overloads. I think this is probably a better decision in the long term, since one might want to support these cases for operators, while warning (or erroring) on the more general cases of implicit conversion.
- This covers matrix/scalar, scalar/matrix, vector/scalar, and scalar/vector cases
Diffstat (limited to 'tests/bugs/gh-103.slang.expected')
| -rw-r--r-- | tests/bugs/gh-103.slang.expected | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/tests/bugs/gh-103.slang.expected b/tests/bugs/gh-103.slang.expected new file mode 100644 index 000000000..acf3026d9 --- /dev/null +++ b/tests/bugs/gh-103.slang.expected @@ -0,0 +1,49 @@ +result code = 0 +standard error = { +} +standard output = { +// +// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384 +// +// +// Buffer Definitions: +// +// cbuffer C +// { +// +// float4x4 a; // Offset: 0 Size: 64 +// float b; // Offset: 64 Size: 4 +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim Slot Elements +// ------------------------------ ---------- ------- ----------- ---- -------- +// C cbuffer NA NA 0 1 +// +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// no Input +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// SV_Target 0 xyzw 0 TARGET float xyzw +// +ps_4_0 +dcl_constantbuffer cb0[5], immediateIndexed +dcl_output o0.xyzw +mul o0.x, cb0[0].x, cb0[4].x +mul o0.y, cb0[1].x, cb0[4].x +mul o0.z, cb0[2].x, cb0[4].x +mul o0.w, cb0[3].x, cb0[4].x +ret +// Approximately 5 instruction slots used +} |
