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| author | James Helferty (NVIDIA) <jhelferty@nvidia.com> | 2025-06-10 11:02:38 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-06-10 10:02:38 -0500 |
| commit | e37202002276b679c5241b2678af612552b06d2c (patch) | |
| tree | dd072338524507cad6db45b28b976d0fbb6dd57a /docs/user-guide/a2-target-specific-features.md | |
| parent | 954ad3d5466219eab216add0cb1ac920da548425 (diff) | |
Fix IR layout of 3-element vectors in cbuffers for -fvk-use-dx-layout (#7282)
* Better handling for 16-byte boundary of d3d cbuffer
Fixes #6921
D3D cbuffers have slightly different packing rules that allow packing
vectors into a 16-byte slot at element alignments, except when
a field would cross a 16-byte boundary. In that case, we need to
realign the field to the next 16-byte boundary.
In particular, this impacts vec3s, which are not a power of two in
size and thus require slightly different alignment logic, compared to
std430 and std140. (Example: a float and float3 should fit together in
that order in a single slot.)
Adds test cases.
Adds documentation page for GLSL target
Diffstat (limited to 'docs/user-guide/a2-target-specific-features.md')
| -rw-r--r-- | docs/user-guide/a2-target-specific-features.md | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/docs/user-guide/a2-target-specific-features.md b/docs/user-guide/a2-target-specific-features.md index 495148c49..7949a00db 100644 --- a/docs/user-guide/a2-target-specific-features.md +++ b/docs/user-guide/a2-target-specific-features.md @@ -11,6 +11,7 @@ In this chapter: 1. [SPIR-V target specific](./a2-01-spirv-target-specific.md) 2. [Metal target specific](./a2-02-metal-target-specific.md) 3. [WGSL target specific](./a2-03-wgsl-target-specific.md) +4. [GLSL target specific](./a2-04-glsl-target-specific.md) <!-- RTD-TOC-START ```{toctree} |
