From 7a4757d2e97f92aae3ddb5dc353a54f72e23351e Mon Sep 17 00:00:00 2001
From: ArielG-NV <159081215+ArielG-NV@users.noreply.github.com>
Date: Wed, 12 Jun 2024 12:39:58 -0400
Subject: Implicit register binding for hlsl to non-hlsl targets (#4338)

* implicit register binding for hlsl to non-hlsl targets

* fix regressions

only warn once with `_maybeDiagnoseMissingVulkanLayoutModifier`

remove unneeded else

* address review and change bindings

address review comments on testing to make the tests indiscriminate over order of code emitted.

Change bindings to 1:1 map to vulkan bindings

* don't set bindings 1:1 with vulkan if command line option was added

---------

Co-authored-by: Yong He <yonghe@outlook.com>
---
 tests/hlsl/register-syntax.slang | 49 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 tests/hlsl/register-syntax.slang

(limited to 'tests/hlsl')

diff --git a/tests/hlsl/register-syntax.slang b/tests/hlsl/register-syntax.slang
new file mode 100644
index 000000000..f3633028d
--- /dev/null
+++ b/tests/hlsl/register-syntax.slang
@@ -0,0 +1,49 @@
+//TEST:SIMPLE(filecheck=CHECK_GLSL): -target glsl -stage compute -entry computeMain
+//TEST:SIMPLE(filecheck=CHECK_HLSL): -target hlsl -stage compute -entry computeMain
+
+//CHECK_GLSL-DAG: binding = 4, set = 2
+//CHECK_GLSL-DAG: binding = 5, set = 1
+//CHECK_GLSL-DAG: binding = 6
+//CHECK_GLSL-DAG: binding = 7
+//CHECK_GLSL-DAG: binding = 15
+//CHECK_GLSL-DAG: binding = 12
+
+//CHECK_HLSL-DAG: u4, space2
+//CHECK_HLSL-DAG: u5, space1
+//CHECK_HLSL-DAG: u6
+//CHECK_HLSL-DAG: u7
+//CHECK_HLSL-DAG: u9
+//CHECK_HLSL-DAG: u12
+
+[[vk::binding(4,2)]]
+RWStructuredBuffer<int> b0 : register(u4, space2);
+
+RWStructuredBuffer<int> b1 : register(u5, space1);
+
+RWStructuredBuffer<int> b2 : register(u6);
+
+[[vk::binding(7,0)]]
+RWStructuredBuffer<int> b3 : register(u7, space0);
+
+[[vk::binding(15,0)]]
+RWStructuredBuffer<int> b4[2] : register(u9);
+
+RWStructuredBuffer<int> b5[2] : register(u12);
+
+[numthreads(1, 1, 1)]
+void computeMain(int3 dispatchThreadID : SV_DispatchThreadID)
+{
+	int tid = dispatchThreadID.x;
+	b0[0] = 1;
+    
+    b1[0] = 1;
+    
+    b2[0] = 1;
+    
+    b3[0] = 1;
+    
+    b4[0][0] = 1;
+    b4[0][1] = 1;
+
+    b5[0][1] = 1;
+}
-- 
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