From 6907ea5c8f83712f40fbc7713de4f4bb656c6c35 Mon Sep 17 00:00:00 2001 From: Jay Kwak <82421531+jkwak-work@users.noreply.github.com> Date: Tue, 6 May 2025 00:27:00 +0000 Subject: Add a new capability hlsl_2018 that avoid using select/and/or (#7003) Co-authored-by: Yong He --- tests/compute/logic-no-short-circuit-evaluation.slang | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'tests/compute') diff --git a/tests/compute/logic-no-short-circuit-evaluation.slang b/tests/compute/logic-no-short-circuit-evaluation.slang index 74351a505..ea2b7a0c3 100644 --- a/tests/compute/logic-no-short-circuit-evaluation.slang +++ b/tests/compute/logic-no-short-circuit-evaluation.slang @@ -1,4 +1,5 @@ //TEST(compute):SIMPLE(filecheck=SM5):-target hlsl -profile cs_5_1 -entry computeMain +//TEST(compute):SIMPLE(filecheck=HLSL2018):-target hlsl -profile cs_6_0 -capability hlsl_2018 -entry computeMain //TEST(compute):SIMPLE(filecheck=SM6):-target hlsl -profile cs_6_0 -entry computeMain //TEST(compute):SIMPLE(filecheck=WGS):-target wgsl -stage compute -entry computeMain //TEST(compute):SIMPLE(filecheck=MTL):-target metal -stage compute -entry computeMain @@ -29,6 +30,7 @@ void computeMain(int3 dispatchThreadID : SV_DispatchThreadID) // No short-circuiting for vector types //SM5:(all({{.*}}&& + //HLSL2018:(all({{.*}}&& //SM6:(all(and( //WGS:(all(select(vec2(false), //MTL:(all({{.*}}&& @@ -40,6 +42,7 @@ void computeMain(int3 dispatchThreadID : SV_DispatchThreadID) // Intentionally using non-boolean type for testing. //SM5:(all({{.*}}|| + //HLSL2018:(all({{.*}}|| //SM6:(or(vector( //WGS:(select({{.*}}, vec2(true), vec2( //MTL:(all(bool2({{.*}}|| @@ -49,6 +52,7 @@ void computeMain(int3 dispatchThreadID : SV_DispatchThreadID) } //SM5:(all({{.*}}?{{.*}}: + //HLSL2018:(all({{.*}}?{{.*}}: //SM6:(all(select( //WGS:(all(select(vec2(false), //MTL:(all(select(bool2(false) -- cgit v1.2.3