From 88382ac7f3eda671c21dadb5b37bfd305369f750 Mon Sep 17 00:00:00 2001 From: Jay Kwak <82421531+jkwak-work@users.noreply.github.com> Date: Fri, 28 Jun 2024 20:38:15 -0700 Subject: Implement CheckAccessFullyMapped (#4509) * Implement CheckAccessFullyMapped Closes #4438 Closes #4445 Closes #1712 Related to #4495 This commit implements "CheckAccessFullyMapped()" for HLSL target. All of other "status" variants for Sample/Load are limited to HLSL by the capability system, because they not properly implemented yet. --- source/slang/hlsl.meta.slang | 114 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 97 insertions(+), 17 deletions(-) (limited to 'source') diff --git a/source/slang/hlsl.meta.slang b/source/slang/hlsl.meta.slang index 8509b4005..7c65aec5e 100644 --- a/source/slang/hlsl.meta.slang +++ b/source/slang/hlsl.meta.slang @@ -113,7 +113,15 @@ struct ByteAddressBuffer } [__readNone] - uint Load(int location, out uint status); + [ForceInline] + [require(hlsl, byteaddressbuffer)] + uint Load(int location, out uint status) + { + __target_switch + { + case hlsl: __intrinsic_asm ".Load"; + } + } [__readNone] [ForceInline] @@ -155,7 +163,15 @@ struct ByteAddressBuffer } [__readNone] - uint2 Load2(int location, out uint status); + [ForceInline] + [require(hlsl, byteaddressbuffer)] + uint2 Load2(int location, out uint status) + { + __target_switch + { + case hlsl: __intrinsic_asm ".Load2"; + } + } [__readNone] [ForceInline] @@ -197,7 +213,15 @@ struct ByteAddressBuffer } [__readNone] - uint3 Load3(int location, out uint status); + [ForceInline] + [require(hlsl, byteaddressbuffer)] + uint3 Load3(int location, out uint status) + { + __target_switch + { + case hlsl: __intrinsic_asm ".Load3"; + } + } [__readNone] [ForceInline] @@ -239,7 +263,15 @@ struct ByteAddressBuffer } [__readNone] - uint4 Load4(int location, out uint status); + [ForceInline] + [require(hlsl, byteaddressbuffer)] + uint4 Load4(int location, out uint status) + { + __target_switch + { + case hlsl: __intrinsic_asm ".Load4"; + } + } [__readNone] [ForceInline] @@ -691,7 +723,7 @@ extension __TextureImpl [__readNone] [ForceInline] - [require(cpp_glsl_hlsl_metal_spirv, texture_sm_4_0_fragment)] + [require(hlsl, texture_sm_4_0_fragment)] T Sample(vector location, vector offset, float clamp, out uint status) { __target_switch @@ -1296,7 +1328,7 @@ extension __TextureImpl [__readNone] [ForceInline] - [require(cpp_glsl_hlsl_metal_spirv, texture_sm_4_0_fragment)] + [require(hlsl, texture_sm_4_0_fragment)] T Sample(SamplerState s, vector location, constexpr vector offset, float clamp, out uint status) { __target_switch @@ -2504,7 +2536,7 @@ extension __TextureImpl location, constexpr vector offset, out uint status) { __target_switch @@ -2670,7 +2702,7 @@ extension __TextureImpl location, int sampleIndex, constexpr vector offset, out uint status) { __target_switch @@ -2869,7 +2901,7 @@ extension __TextureImpl location, vector offset, out uint status) { __target_switch @@ -3092,6 +3124,7 @@ extension __TextureImpl location, int sampleIndex, vector offset, out uint status) { __target_switch @@ -3764,7 +3797,7 @@ struct StructuredBuffer T Load(TIndex location); __intrinsic_op($(kIROp_StructuredBufferLoadStatus)) - [require(cpp_cuda_glsl_hlsl_spirv, structuredbuffer)] + [require(hlsl, structuredbuffer)] T Load(TIndex location, out uint status); __generic @@ -3894,7 +3927,15 @@ struct $(item.name) } [__NoSideEffect] - uint Load(int location, out uint status); + [ForceInline] + [require(hlsl, byteaddressbuffer_rw)] + uint Load(int location, out uint status) + { + __target_switch + { + case hlsl: __intrinsic_asm ".Load"; + } + } [__NoSideEffect] [ForceInline] @@ -3936,7 +3977,15 @@ struct $(item.name) } [__NoSideEffect] - uint2 Load2(int location, out uint status); + [ForceInline] + [require(hlsl, byteaddressbuffer_rw)] + uint2 Load2(int location, out uint status) + { + __target_switch + { + case hlsl: __intrinsic_asm ".Load2"; + } + } [__NoSideEffect] [ForceInline] @@ -3978,7 +4027,15 @@ struct $(item.name) } [__NoSideEffect] - uint3 Load3(int location, out uint status); + [ForceInline] + [require(hlsl, byteaddressbuffer_rw)] + uint3 Load3(int location, out uint status) + { + __target_switch + { + case hlsl: __intrinsic_asm ".Load3"; + } + } [__NoSideEffect] [ForceInline] @@ -4020,7 +4077,15 @@ struct $(item.name) } [__NoSideEffect] - uint4 Load4(int location, out uint status); + [ForceInline] + [require(hlsl, byteaddressbuffer_rw)] + uint4 Load4(int location, out uint status) + { + __target_switch + { + case hlsl: __intrinsic_asm ".Load4"; + } + } [__NoSideEffect] [ForceInline] @@ -6636,7 +6701,15 @@ T copysign(T x, T y) // Check access status to tiled resource -bool CheckAccessFullyMapped(uint status); +[ForceInline] +[require(hlsl, sm_5_0)] +bool CheckAccessFullyMapped(out uint status) +{ + __target_switch + { + case hlsl: __intrinsic_asm "CheckAccessFullyMapped"; + } +} // Clamp (HLSL SM 1.0) __generic @@ -15179,6 +15252,7 @@ for (int aa = 0; aa < kBaseBufferAccessLevelCount; ++aa) char const* spvLoadInstName = (isReadOnly) ? "OpImageFetch" : "OpImageRead"; char const* requireToSetQuery = (isReadOnly) ? "[require(glsl_hlsl_metal_spirv, texture_size)]" : "[require(glsl_hlsl_metal_spirv, image_size)]"; char const* requireToSet = (isReadOnly) ? "[require(glsl_hlsl_metal_spirv, texture_sm_4_1)]" : "[require(glsl_hlsl_metal_spirv, texture_sm_4_1_compute_fragment)]"; + char const* requireToSet_onlyHLSL = (isReadOnly) ? "[require(hlsl, texture_sm_4_1)]" : "[require(hlsl, texture_sm_4_1_compute_fragment)]"; }}}} __generic @@ -15219,8 +15293,14 @@ extension __TextureImpl } $(isReadOnly?"[__readNone] ":"") - $(requireToSet) - T Load(int location, out uint status); + $(requireToSet_onlyHLSL) + T Load(int location, out uint status) + { + __target_switch + { + case hlsl: __intrinsic_asm ".Load"; + } + } __subscript(uint index) -> T { -- cgit v1.2.3