From 14f4b45d4b977805c5dbe472e327bdd3e856fb94 Mon Sep 17 00:00:00 2001 From: Yong He Date: Sun, 27 Oct 2024 09:40:17 -0700 Subject: Add `InterlockedAddF64` intrinsic. (#5412) --- docs/user-guide/a3-02-reference-capability-atoms.md | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'docs/user-guide') diff --git a/docs/user-guide/a3-02-reference-capability-atoms.md b/docs/user-guide/a3-02-reference-capability-atoms.md index f8f1b8eb7..9f673eaf8 100644 --- a/docs/user-guide/a3-02-reference-capability-atoms.md +++ b/docs/user-guide/a3-02-reference-capability-atoms.md @@ -407,6 +407,9 @@ Extensions `spvAtomicFloat16AddEXT` > Represents the SPIR-V capability for atomic float 16 add operations. +`spvAtomicFloat64AddEXT` +> Represents the SPIR-V capability for atomic float 64 add operations. + `spvInt64Atomics` > Represents the SPIR-V capability for 64-bit integer atomics. @@ -416,6 +419,9 @@ Extensions `spvAtomicFloat16MinMaxEXT` > Represents the SPIR-V capability for atomic float 16 min/max operations. +`spvAtomicFloat64MinMaxEXT` +> Represents the SPIR-V capability for atomic float 64 min/max operations. + `spvDerivativeControl` > Represents the SPIR-V capability for 'derivative control' operations. @@ -684,6 +690,9 @@ Compound Capabilities `cpp_cuda_spirv` > CPP, CUDA and SPIRV code-gen targets +`cuda_spirv` +> CUDA and SPIRV code-gen targets + `cpp_cuda_glsl_spirv` > CPP, CUDA, GLSL and SPIRV code-gen targets -- cgit v1.2.3