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<title>slang.git/source/slang/slang-ir-layout.h, branch master</title>
<subtitle>Making it easier to work with shaders</subtitle>
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<updated>2025-08-21T05:47:18+00:00</updated>
<entry>
<title>Introduce CDataLayout &amp; -fvk-use-c-layout (#8136)</title>
<updated>2025-08-21T05:47:18+00:00</updated>
<author>
<name>Julius Ikkala</name>
<email>julius.ikkala@gmail.com</email>
</author>
<published>2025-08-21T05:47:18+00:00</published>
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<id>urn:sha1:35f8e092f2aa3ed5e3cf03387e712f798ff4850e</id>
<content type='text'>
Closes #8112. ~~The issue asks for a "C layout", but in this PR I use
the term "CPU layout" because this naming was pre-existing in the
codebase as `kCPULayoutRulesImpl_`. The primary purpose of this layout
is to match CPU-side struct definitions with the shader side. I'm open
to better naming suggestions, though.~~

Edit: switched back to using `CDataLayout` &amp; `-fvk-use-c-layout`, as the
CPU target depends on the object layout rules of existing CPU layout
rules, but they're incompatible with actual shaders. So a new
`kCLayoutRulesImpl_` was needed anyway.

---------

Co-authored-by: Ellie Hermaszewska &lt;ellieh@nvidia.com&gt;</content>
</entry>
<entry>
<title>Fix IR layout of 3-element vectors in cbuffers for -fvk-use-dx-layout (#7282)</title>
<updated>2025-06-10T15:02:38+00:00</updated>
<author>
<name>James Helferty (NVIDIA)</name>
<email>jhelferty@nvidia.com</email>
</author>
<published>2025-06-10T15:02:38+00:00</published>
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<id>urn:sha1:e37202002276b679c5241b2678af612552b06d2c</id>
<content type='text'>
* Better handling for 16-byte boundary of d3d cbuffer

Fixes #6921

D3D cbuffers have slightly different packing rules that allow packing
vectors into a 16-byte slot at element alignments, except when
a field would cross a 16-byte boundary. In that case, we need to
realign the field to the next 16-byte boundary.

In particular, this impacts vec3s, which are not a power of two in
size and thus require slightly different alignment logic, compared to
std430 and std140. (Example: a float and float3 should fit together in
that order in a single slot.)

Adds test cases.

Adds documentation page for GLSL target</content>
</entry>
<entry>
<title>format</title>
<updated>2024-10-29T06:49:26+00:00</updated>
<author>
<name>Ellie Hermaszewska</name>
<email>ellieh@nvidia.com</email>
</author>
<published>2024-10-29T06:49:26+00:00</published>
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<id>urn:sha1:f65d756bff8d4c5cbc15bd0322a2ae8e6b896a21</id>
<content type='text'>
* format

* Minor test fixes

* enable checking cpp format in ci</content>
</entry>
<entry>
<title>Implement `-fvk-use-dx-layout` (#4912)</title>
<updated>2024-08-26T19:11:41+00:00</updated>
<author>
<name>ArielG-NV</name>
<email>159081215+ArielG-NV@users.noreply.github.com</email>
</author>
<published>2024-08-26T19:11:41+00:00</published>
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<id>urn:sha1:e1c6fecd90142761aaecbf4e281beb87893fc531</id>
<content type='text'>
* Implement `-fvk-use-dx-layout`

Fixes: #4126

Changes:
* Added fvk-use-dx-layout
* Modified `HLSLConstantBufferLayoutRulesImpl` for correctness (ex: Array is always 16 byte aligned)
* Added kFXCShaderResourceLayoutRulesFamilyImpl and kFXCConstantBufferLayoutRulesFamilyImpl to handle fvk-use-dx-layout
* Added `ConstantBufferLayoutRules` to manage constant buffer rules
* Added `alignCompositeElementOfNonAggregate`/`alignCompositeElementOfAggregate` to handle forced alignment of composites for ConstantBuffers
* `StructuredBuffer` rules are mostly equal to `scalar` layout, not much was needed to be changed to support this behavior.

* seperate legacy constant buffer and how Slang does constant-buffer normally

* undo an addition

* remove accidental test

* Address review and fix

Address review and remove GLSL support since GLSL requires a seperate legalization (need to linearlize structs like with `legalizeMetalIR` to assign explicit offsets)

* comments

* remove aggregate and non-aggregate logic

We don't need this distinction for the logic

---------

Co-authored-by: Yong He &lt;yonghe@outlook.com&gt;</content>
</entry>
<entry>
<title>Refactor compiler option representations. (#3598)</title>
<updated>2024-02-20T20:24:00+00:00</updated>
<author>
<name>Yong He</name>
<email>yonghe@outlook.com</email>
</author>
<published>2024-02-20T20:24:00+00:00</published>
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<id>urn:sha1:4d20fd329956ac89408b1628a8291fea01bc9a6d</id>
<content type='text'>
* Refactor compiler option representation.

* Fix binary compatibility.

* Add a test for specifying compiler options at link time.

* Fix binary compatibility.

* Fix binary compatibility.

* Fix backward compatibility on matrix layout.

* Fix.

* Fix.

* Fix.

* Fix gfx.

* Fix gfx.

* Fix dynamic dispatch.

* Polish.</content>
</entry>
<entry>
<title>GLSL Passthrough support for SSBO types (#3446)</title>
<updated>2024-02-03T02:14:04+00:00</updated>
<author>
<name>Ellie Hermaszewska</name>
<email>ellieh@nvidia.com</email>
</author>
<published>2024-02-03T02:14:04+00:00</published>
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<id>urn:sha1:a67cb0609587c230746b52567ff5775cab215220</id>
<content type='text'>
* GLSL Passthrough support for SSBO types

* GLSL Passthrough support for SSBO types

* Correctly apply glsl local size layout to entry points during lowering

* Test for glsl layout correctness

* typo

* Reflect GLSL SSBO as raw buffers

* Functional test for glsl ssbo

* Allow allow glsl for render tests

* Functional test for ssbo passthrough

* Functional test for ssbo passthrough with spirv-direct

* fix windows build error

---------

Co-authored-by: Yong He &lt;yonghe@outlook.com&gt;</content>
</entry>
<entry>
<title>Use target-dependent pointer size in natural layout. (#3210)</title>
<updated>2023-09-19T03:46:57+00:00</updated>
<author>
<name>Yong He</name>
<email>yonghe@outlook.com</email>
</author>
<published>2023-09-19T03:46:57+00:00</published>
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<id>urn:sha1:d1efc69a20d941116d1398e4471689658cd6b888</id>
<content type='text'>
Co-authored-by: Yong He &lt;yhe@nvidia.com&gt;</content>
</entry>
<entry>
<title>Add SPIRV atomics intrinsics and fix buffer layout lowering. (#3170)</title>
<updated>2023-08-31T20:49:40+00:00</updated>
<author>
<name>Yong He</name>
<email>yonghe@outlook.com</email>
</author>
<published>2023-08-31T20:49:40+00:00</published>
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<id>urn:sha1:cc412af89e54b04ead508ca84825a18d001b92d0</id>
<content type='text'>
* Fix atomics intrinsics and buffer layout lowering.

* Fix.

* Add more test.

* Fix.

---------

Co-authored-by: Yong He &lt;yhe@nvidia.com&gt;</content>
</entry>
<entry>
<title>Create storage types of different layouts for SPIRV emit. (#3116)</title>
<updated>2023-08-17T05:47:35+00:00</updated>
<author>
<name>Yong He</name>
<email>yonghe@outlook.com</email>
</author>
<published>2023-08-17T05:47:35+00:00</published>
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<id>urn:sha1:216fc18661fd6e05053b4cc864396e6017e85b04</id>
<content type='text'>
* Create storage types of different layouts for SPIRV emit.

* Fix.

* Fix.

* Fix.

* Update expected failure list.

---------

Co-authored-by: Yong He &lt;yhe@nvidia.com&gt;</content>
</entry>
<entry>
<title>Support `-fvk-use-gl-layout` for ByteAddressBuffer load/store. (#3068)</title>
<updated>2023-08-08T20:54:05+00:00</updated>
<author>
<name>Yong He</name>
<email>yonghe@outlook.com</email>
</author>
<published>2023-08-08T20:54:05+00:00</published>
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<id>urn:sha1:ea1f1653896163d0f3aadc35f7fedf3d8102a71b</id>
<content type='text'>
* Support `-fvk-use-gl-layout` for ByteAddressBuffer load/store.

* Fix.

* Fix.

* Add test for unaligned load.

---------

Co-authored-by: Yong He &lt;yhe@nvidia.com&gt;</content>
</entry>
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