slang.git/source/slang/slang-ir-extract-value-from-type.cpp, branch masterMaking it easier to work with shadershttps://git.yummers.dev/slang.git/atom?h=master2025-07-17T08:46:12+00:00Fix BitCast emitting bit shifts with too small integer types (#7792)2025-07-17T08:46:12+00:00Julius Ikkalajulius.ikkala@gmail.com2025-07-17T08:46:12+00:00urn:sha1:b138e3f4b64e8f096c30d200dbafc701f0da6356
Co-authored-by: Yong He <yonghe@outlook.com>bitcast require the input has same width with result type (#7018)2025-05-07T05:46:42+00:00kaizhangNV149626564+kaizhangNV@users.noreply.github.com2025-05-07T05:46:42+00:00urn:sha1:ccdb2e39da37753961f3694d0f90e676bf859006
bitcast requires the input has same width with result type, this PR ensures that we always lower the bitcast IR instruction satisfies this requirement.
Close #7017.
Add interger pack/unpack intrinsic to glsl (#6997)2025-05-06T15:51:07+00:00kaizhangNV149626564+kaizhangNV@users.noreply.github.com2025-05-06T15:51:07+00:00urn:sha1:10376faffee1ab51b2d23c311212b5724c3c6ac6
* Add interger pack/unpack intrinsic to glsl
Add unpack8, unpack16 and pack32 intrinsics to glsl.
* add unit test
* fix lowering logic for 'bitcast'
* formatFix reinterpret and bitcast and generic arg parsing. (#6627)2025-03-19T18:44:04+00:00Yong Heyonghe@outlook.com2025-03-19T18:44:04+00:00urn:sha1:4eb7a27ac4532a49b9d383d2b0d80bc0ec317b4c
* Fix reinterpret and bitcast.
* Fix warning.
* Fix.
* Fix.
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Co-authored-by: Ellie Hermaszewska <ellieh@nvidia.com>Move switch statement bodies to their own lines (#5493)2024-11-05T17:47:26+00:00Ellie Hermaszewskaellieh@nvidia.com2024-11-05T17:47:26+00:00urn:sha1:b118451e301d734e3e783b3acdf871f3f6ea851c
* Move switch statement bodies to their own lines
* format
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Co-authored-by: Yong He <yonghe@outlook.com>format2024-10-29T06:49:26+00:00Ellie Hermaszewskaellieh@nvidia.com2024-10-29T06:49:26+00:00urn:sha1:f65d756bff8d4c5cbc15bd0322a2ae8e6b896a21
* format
* Minor test fixes
* enable checking cpp format in ciRefactor compiler option representations. (#3598)2024-02-20T20:24:00+00:00Yong Heyonghe@outlook.com2024-02-20T20:24:00+00:00urn:sha1:4d20fd329956ac89408b1628a8291fea01bc9a6d
* Refactor compiler option representation.
* Fix binary compatibility.
* Add a test for specifying compiler options at link time.
* Fix binary compatibility.
* Fix binary compatibility.
* Fix backward compatibility on matrix layout.
* Fix.
* Fix.
* Fix.
* Fix gfx.
* Fix gfx.
* Fix dynamic dispatch.
* Polish.Use target-dependent pointer size in natural layout. (#3210)2023-09-19T03:46:57+00:00Yong Heyonghe@outlook.com2023-09-19T03:46:57+00:00urn:sha1:d1efc69a20d941116d1398e4471689658cd6b888
Co-authored-by: Yong He <yhe@nvidia.com>Create storage types of different layouts for SPIRV emit. (#3116)2023-08-17T05:47:35+00:00Yong Heyonghe@outlook.com2023-08-17T05:47:35+00:00urn:sha1:216fc18661fd6e05053b4cc864396e6017e85b04
* Create storage types of different layouts for SPIRV emit.
* Fix.
* Fix.
* Fix.
* Update expected failure list.
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Co-authored-by: Yong He <yhe@nvidia.com>Add an accessor for IRInst opcode (#1707)2021-02-16T19:48:21+00:00Tim FoleytfoleyNV@users.noreply.github.com2021-02-16T19:48:21+00:00urn:sha1:e474c4e3aadc22a1b9f9b006104409f10936244f
* Add an accessor for IRInst opcode
This main changing is renaming `IRInst::op` over to `IRInst::m_op` and then adds an accessor `IRInst::getOp()` to read it. The rest of the changes are just changing use sites to `getOp` (or to `m_op` in the limited cases where we write to it).
This work is in anticipation of a future change that might need to store an extra bit in the same field as the opcode. It seemed better to do this massive refactoring as a separate PR.
* fixup